Hello thin chips
6 Dec 2001
Fujitsu Limited has developed a new chemical-free process technology that enables the production of silicon chips that are only 25 µm thick, or one-fourth the thickness of existing chips.
The technology represents a significant contribution to the effort to reduce the thickness of packages that contain multiple stacked chips, such as system-in-package and multi-chip package (MCP) designs. Moreover, because this process technology forgoes the use of chemicals in chip polishing, it reduces processing time, equipment costs and environmental impact.
With higher functionality being built into wireless phones, digital AV appliances and integrated circuit (IC) cards, there is increasing demand for smaller, thinner, and more densely integrated chips to drive them. Despite advances such as chip-scale packages (CSP) and multiple chips in a single package, as in MCP, the demand for ever-thinner chips persists.
Generally, chips for thin profile products must have thickness of 150 µm or less, while chips for CSPs and MCPs must be 100 µm or less, and for IC cards, 50 µm or less.
At present, chips can be reduced to a thickness in the range of 100 to 150 µm using a chemical-free polishing process. However, when polishing chips thinner than 100 µm without using chemicals, the residual pressure and powder from the process can crack the wafer. While chemicals can be used to achieve thicknesses 100 µm and under, their usage increases processing time, equipment costs, and problems associated with environmental emissions.
Fujitsu has now resolved these problems with the development of a wafer support technology that can be integrated with the pick-up process. With this wafer technology, the wafer is fixed in a jig that corrects for any warping that occurs in the polishing of the wafer's underside. The shape, materials, and construction of the wafer support jig were all carefully considered to ensure that the chip's featured surface is held steady. This technology can be deployed simply by adding the jig to existing equipment, obviating the need for costly new equipment.
Also, since this technology is optimised to integrate with the pick-up process after the wafer has been separated into separate chips (dicing), the chips come off the protective tape gradually, which reduces damage to the chip.
The process technology was developed with the technical assistance of Tokyo-based Disco.
